The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2009

Filed:

Oct. 26, 2007
Applicants:

Mitul B. Modi, Phoenix, AZ (US);

Patricia A. Brusso, Chandler, AZ (US);

Ruben Cadena, Tempe, AZ (US);

Carolyn R. Mccormick, Chandler, AZ (US);

Sankara J. Subramanian, Chandler, AZ (US);

Inventors:

Mitul B. Modi, Phoenix, AZ (US);

Patricia A. Brusso, Chandler, AZ (US);

Ruben Cadena, Tempe, AZ (US);

Carolyn R. McCormick, Chandler, AZ (US);

Sankara J. Subramanian, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H05K 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.


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