The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2009

Filed:

Jul. 25, 2008
Applicants:

Hiroyuki Akatsu, Yorktown Heights, NY (US);

Rama Divakaruni, Ossining, NY (US);

Gregory G. Freeman, Hopewell Junction, NY (US);

David R. Greenberg, White Plains, NY (US);

Marwan H. Khater, Poughkeepsie, NY (US);

William R. Tonti, Essex Junction, VT (US);

Inventors:

Hiroyuki Akatsu, Yorktown Heights, NY (US);

Rama Divakaruni, Ossining, NY (US);

Gregory G. Freeman, Hopewell Junction, NY (US);

David R. Greenberg, White Plains, NY (US);

Marwan H. Khater, Poughkeepsie, NY (US);

William R. Tonti, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 27/102 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.


Find Patent Forward Citations

Loading…