The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Mar. 31, 2006
Francois J. Henley, Aptos, CA (US);
James Andrew Sullivan, Woodside, CA (US);
Sien Giok Kang, Dublin, CA (US);
Philip James Ong, Milpitas, CA (US);
Harry Robert Kirk, Campbell, CA (US);
David Jacy, San Jose, CA (US);
Igor Malik, Palo Alto, CA (US);
Francois J. Henley, Aptos, CA (US);
James Andrew Sullivan, Woodside, CA (US);
Sien Giok Kang, Dublin, CA (US);
Philip James Ong, Milpitas, CA (US);
Harry Robert Kirk, Campbell, CA (US);
David Jacy, San Jose, CA (US);
Igor Malik, Palo Alto, CA (US);
Silicon Genesis Corporation, San Jose, CA (US);
Abstract
A method for fabricating bonded substrate structures, e.g., silicon on silicon. In a specific embodiment, the method includes providing a thickness of single crystal silicon material transferred from a first silicon substrate coupled to a second silicon substrate. In a specific embodiment, the second silicon substrate has a second surface region that is joined to a first surface region from the thickness of single crystal silicon material to form of an interface region having a first characteristic including a silicon oxide material between the thickness of single crystal silicon material and the second silicon substrate. The method includes subjecting the interface region to a thermal process to cause a change to the interface region from the first characteristic to a second characteristic. In a specific embodiment, the second characteristic is free from the silicon oxide material and is an epitaxially formed silicon material provided between the thickness of single crystal silicon material and the second silicon substrate. The method includes maintaining the interface region free of multiple voids during the thermal process to form the epitaxially formed silicon material to electrically couple the thickness of single crystal silicon material to the second silicon substrate.