The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2009
Filed:
Aug. 31, 2007
Daniel C. Edelstein, White Plains, NY (US);
Matthew E. Colburn, Hopewell Junction, NY (US);
Edward C. Cooney, Iii, Jericho, VT (US);
Timothy J. Dalton, Ridgefield, CT (US);
John A. Fitzsimmons, Poughkeepsie, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
Elbert E. Huang, Tarrytown, NY (US);
Michael W. Lane, Cortlandt Manor, NY (US);
Vincent J. Mcgahay, Poughkeepsie, NY (US);
Lee M. Nicholson, Katonah, NY (US);
Satyanarayana V. Nitta, Poughquag, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Sujatha Sankaran, Wappingers Falls, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Anthony K. Stamper, Williston, VT (US);
Daniel C. Edelstein, White Plains, NY (US);
Matthew E. Colburn, Hopewell Junction, NY (US);
Edward C. Cooney, III, Jericho, VT (US);
Timothy J. Dalton, Ridgefield, CT (US);
John A. Fitzsimmons, Poughkeepsie, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
Elbert E. Huang, Tarrytown, NY (US);
Michael W. Lane, Cortlandt Manor, NY (US);
Vincent J. McGahay, Poughkeepsie, NY (US);
Lee M. Nicholson, Katonah, NY (US);
Satyanarayana V. Nitta, Poughquag, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Sujatha Sankaran, Wappingers Falls, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Anthony K. Stamper, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.