The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2009
Filed:
Jul. 25, 2005
Chia-tsung Tso, Hsin-Chu, TW;
Jiun-hong Lai, Hsin-Chu, TW;
Mei-jen Wu, Hsin-Chu, TW;
LI Te Hsu, Shanhua Township, Tainan County, TW;
Pin Chia Su, Tainan, TW;
Po-zen Chen, Kaohsiung, TW;
Chia-Tsung Tso, Hsin-Chu, TW;
Jiun-Hong Lai, Hsin-Chu, TW;
Mei-Jen Wu, Hsin-Chu, TW;
Li Te Hsu, Shanhua Township, Tainan County, TW;
Pin Chia Su, Tainan, TW;
Po-Zen Chen, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.