The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Feb. 25, 2008
Peng Soon Lim, Melaka, MY;
Terh Kuen Yii, Kuala Lumpur, MY;
You Chye How, Melaka, MY;
Sek Hoi Chong, Melaka, MY;
Shee Min Yeong, Melaka, MY;
Peng Soon Lim, Melaka, MY;
Terh Kuen Yii, Kuala Lumpur, MY;
You Chye How, Melaka, MY;
Sek Hoi Chong, Melaka, MY;
Shee Min Yeong, Melaka, MY;
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.