The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Dec. 08, 2005
Cha-won Koh, Yongin-si, KR;
Sang-gyun Woo, Yongin-si, KR;
Seok-hwan OH, Yongin-si, KR;
Gi-sung Yeo, Seoul, KR;
Hyun-jae Kang, Gunpo-si, KR;
Jang-ho Shin, Seoul, KR;
Cha-Won Koh, Yongin-si, KR;
Sang-Gyun Woo, Yongin-si, KR;
Seok-Hwan Oh, Yongin-si, KR;
Gi-Sung Yeo, Seoul, KR;
Hyun-Jae Kang, Gunpo-si, KR;
Jang-Ho Shin, Seoul, KR;
Abstract
There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.