The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Jan. 24, 2008
Derryl D. J. Allman, Camas, WA (US);
Hemanshu D. Bhatt, Vancouver, WA (US);
Charles E. May, Fairview, OR (US);
Peter Austin Burke, Portland, OR (US);
Byung-sung Kwak, Portland, OR (US);
Sey-shing Sun, Portland, OR (US);
David T. Price, Gresham, OR (US);
David Pritchard, Saxony, DE;
Derryl D. J. Allman, Camas, WA (US);
Hemanshu D. Bhatt, Vancouver, WA (US);
Charles E. May, Fairview, OR (US);
Peter Austin Burke, Portland, OR (US);
Byung-Sung Kwak, Portland, OR (US);
Sey-Shing Sun, Portland, OR (US);
David T. Price, Gresham, OR (US);
David Pritchard, Saxony, DE;
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.