The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Nov. 14, 2006
Linh Dang, Lawndale, CA (US);
Wayne Yoshida, Hermosa Beach, CA (US);
Gerry Mei, Manhattan Beach, CA (US);
Jennifer Wang, Redondo Beach, CA (US);
Po-hsin Liu, Anaheim, CA (US);
Jane Lee, Torrance, CA (US);
Weidong Liu, San Marino, CA (US);
Mike Barsky, Sherman Oaks, CA (US);
Rich Lai, Redondo Beach, CA (US);
Linh Dang, Lawndale, CA (US);
Wayne Yoshida, Hermosa Beach, CA (US);
Gerry Mei, Manhattan Beach, CA (US);
Jennifer Wang, Redondo Beach, CA (US);
Po-Hsin Liu, Anaheim, CA (US);
Jane Lee, Torrance, CA (US);
Weidong Liu, San Marino, CA (US);
Mike Barsky, Sherman Oaks, CA (US);
Rich Lai, Redondo Beach, CA (US);
Northrop Grumman Space & Mission Systems Corp., Los Angeles, CA (US);
Abstract
In a method of forming a semiconductor device on a semiconductor substrate (), a photoresist layer () is deposited on the semiconductor substrate; a window () is formed in the photoresist layer () by electron beam lithography; a conformal layer () is deposited on the photoresist layer () and in the window (); and substantially all of the conformal layer () is selectively removed from the photoresist layer () and a bottom portion of the window to form dielectric sidewalls () in the window ().