The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2009
Filed:
May. 22, 2006
Chih-hsin Ko, Fongshan, TW;
Chung-hu KE, Taipei, TW;
Hung-wei Chen, Hsinchu, TW;
Wen-chin Lee, Hsin-Chu, TW;
Chih-Hsin Ko, Fongshan, TW;
Chung-Hu Ke, Taipei, TW;
Hung-Wei Chen, Hsinchu, TW;
Wen-Chin Lee, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.