The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2009
Filed:
Sep. 25, 2006
Satoshi Isa, Tokyo, JP;
Satoshi Itaya, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Fumiyuki Osanai, Tokyo, JP;
Hiroki Fujisawa, Tokyo, JP;
Satoshi Isa, Tokyo, JP;
Satoshi Itaya, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Fumiyuki Osanai, Tokyo, JP;
Hiroki Fujisawa, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.