The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2009
Filed:
Mar. 01, 2007
Mantu K. Hudait, Portland, OR (US);
Dmitri Loubychev, Bethlehem, PA (US);
Suman Datta, Beaverton, OR (US);
Robert Chau, Beaverton, OR (US);
Joel M. Fastenau, Bethlehem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Mantu K. Hudait, Portland, OR (US);
Dmitri Loubychev, Bethlehem, PA (US);
Suman Datta, Beaverton, OR (US);
Robert Chau, Beaverton, OR (US);
Joel M. Fastenau, Bethlehem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.