The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2009

Filed:

Sep. 26, 2007
Applicants:

Nima Mokhlesi, Los Gatos, CA (US);

Dengtao Zhao, Sunnyvale, CA (US);

Man Mui, Santa Clara, CA (US);

Hao Nguyen, San Jose, CA (US);

Seungpil Lee, San Ramon, CA (US);

Deepak Chandra Sekar, Atlanta, GA (US);

Tapan Samaddar, Santa Clara, CA (US);

Inventors:

Nima Mokhlesi, Los Gatos, CA (US);

Dengtao Zhao, Sunnyvale, CA (US);

Man Mui, Santa Clara, CA (US);

Hao Nguyen, San Jose, CA (US);

Seungpil Lee, San Ramon, CA (US);

Deepak Chandra Sekar, Atlanta, GA (US);

Tapan Samaddar, Santa Clara, CA (US);

Assignee:

SanDisk Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.


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