The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2009
Filed:
Mar. 20, 2006
Yuji Sonoda, Hiratsuka, JP;
Shuji Kikuchi, Yokohama, JP;
Katsunori Hirano, Yokohama, JP;
Ichiro Anjo, Koganei, JP;
Mitsuaki Katagiri, Nishitokyo, JP;
Yuji Sonoda, Hiratsuka, JP;
Shuji Kikuchi, Yokohama, JP;
Katsunori Hirano, Yokohama, JP;
Ichiro Anjo, Koganei, JP;
Mitsuaki Katagiri, Nishitokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.