The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
Mar. 01, 2004
Todd P. Lukanc, San Jose, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl Babcock, Campbell, CA (US);
Hung-eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Todd P. Lukanc, San Jose, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl Babcock, Campbell, CA (US);
Hung-Eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.