The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
Jul. 17, 2006
Ruediger Schmolke, Burghausen, DE;
Thomas Buschhardt, Burghausen, DE;
Gerhard Heier, Burghausen, DE;
Guido Wenski, Burghausen, DE;
Ruediger Schmolke, Burghausen, DE;
Thomas Buschhardt, Burghausen, DE;
Gerhard Heier, Burghausen, DE;
Guido Wenski, Burghausen, DE;
Siltronic AG, Munich, DE;
Abstract
A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRof less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.