The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2009
Filed:
Apr. 03, 2006
Peter Tolchinsky, Beaverton, OR (US);
Irwin Yablok, Portland, OR (US);
Chuan HU, Chandler, AZ (US);
Richard D. Emery, Chandler, AZ (US);
Peter Tolchinsky, Beaverton, OR (US);
Irwin Yablok, Portland, OR (US);
Chuan Hu, Chandler, AZ (US);
Richard D. Emery, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.