The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Feb. 28, 2006
Hsi-kuei Cheng, Hsin-Chu, TW;
Hung-ju Chien, Hsin-Chu, TW;
Hsun-chang Chan, Hsin-Chu, TW;
Chu-chang Chen, Hsin-Chu, TW;
Ying-lang Wang, Hsin-Chu, TW;
Chin-hao Su, Hsin-Chu, TW;
Hsien-ping Feng, Taipei, TW;
Shih-tzung Chang, Taichung, TW;
Hsi-Kuei Cheng, Hsin-Chu, TW;
Hung-Ju Chien, Hsin-Chu, TW;
Hsun-Chang Chan, Hsin-Chu, TW;
Chu-Chang Chen, Hsin-Chu, TW;
Ying-Lang Wang, Hsin-Chu, TW;
Chin-Hao Su, Hsin-Chu, TW;
Hsien-Ping Feng, Taipei, TW;
Shih-Tzung Chang, Taichung, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.