The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Aug. 08, 2005
Mong Song Liang, Hsin-Chu, TW;
Chien-hao Chen, Chuangwei Township, TW;
Chun-feng Nieh, Baoshan Township, TW;
Pang-yen Tsai, Jhu-bei, TW;
Tze-liang Lee, Hsinchu, TW;
Shih-chang Chen, Hsin-Chu, TW;
Mong Song Liang, Hsin-Chu, TW;
Chien-Hao Chen, Chuangwei Township, TW;
Chun-Feng Nieh, Baoshan Township, TW;
Pang-Yen Tsai, Jhu-bei, TW;
Tze-Liang Lee, Hsinchu, TW;
Shih-Chang Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.