The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Nov. 06, 2006
Yu-chang Jong, Hsinchu, TW;
Ruey-hsin Liu, Hsin-Chu, TW;
Yueh-chiou Lin, Hsinchu, TW;
Shun-liang Hsu, Hsin-Chu, TW;
Chi-hsuen Chang, Hsinchu, TW;
Te-yin Hsia, Taipei, TW;
Yu-Chang Jong, Hsinchu, TW;
Ruey-Hsin Liu, Hsin-Chu, TW;
Yueh-Chiou Lin, Hsinchu, TW;
Shun-Liang Hsu, Hsin-Chu, TW;
Chi-Hsuen Chang, Hsinchu, TW;
Te-Yin Hsia, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.