The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2009
Filed:
Feb. 15, 2006
Sanjay C. Mehta, Poughkeepsie, NY (US);
Daniel C. Edelstein, White Plains, NY (US);
John A. Fitzsimmons, Poughkeepsie, NY (US);
Stephan Grunow, Wappingers Falls, NY (US);
Henry A. Nye, Iii, Brookfield, CT (US);
David L. Rath, Stormville, NY (US);
Sanjay C. Mehta, Poughkeepsie, NY (US);
Daniel C. Edelstein, White Plains, NY (US);
John A. Fitzsimmons, Poughkeepsie, NY (US);
Stephan Grunow, Wappingers Falls, NY (US);
Henry A. Nye, III, Brookfield, CT (US);
David L. Rath, Stormville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via 'anchors' (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration ('drilling, gouging') into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.