The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2009
Filed:
May. 04, 2006
Stephen H. Tang, Pleasanton, CA (US);
Ali Keshavarzi, Portland, OR (US);
Dinesh Somasekhar, Portland, OR (US);
Fabrice Paillet, Hillsboro, OR (US);
Muhammad M. Khellah, Oswego, OR (US);
Yibin YE, Portland, OR (US);
Shih-lien L. LU, Portland, OR (US);
Brian Doyle, Portland, OR (US);
Suman Datta, Beaverton, OR (US);
Vivek K. DE, Beaverton, OR (US);
Stephen H. Tang, Pleasanton, CA (US);
Ali Keshavarzi, Portland, OR (US);
Dinesh Somasekhar, Portland, OR (US);
Fabrice Paillet, Hillsboro, OR (US);
Muhammad M. Khellah, Oswego, OR (US);
Yibin Ye, Portland, OR (US);
Shih-Lien L. Lu, Portland, OR (US);
Brian Doyle, Portland, OR (US);
Suman Datta, Beaverton, OR (US);
Vivek K. De, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.