The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2009
Filed:
Jul. 09, 2003
Osamu Kusumoto, Nara, JP;
Makoto Kitabatake, Nara, JP;
Kunimasa Takahashi, Ibaraki, JP;
Kenya Yamashita, Kadoma, JP;
Ryoko Miyanaga, Nara, JP;
Masao Uchida, Ibaraki, JP;
Osamu Kusumoto, Nara, JP;
Makoto Kitabatake, Nara, JP;
Kunimasa Takahashi, Ibaraki, JP;
Kenya Yamashita, Kadoma, JP;
Ryoko Miyanaga, Nara, JP;
Masao Uchida, Ibaraki, JP;
Panasonic Corporation, Osaka, JP;
Abstract
An accumulation-mode MISFET comprises: a high-resistance SiC layerepitaxially grown on a SiC substrate; a well region; an accumulation channel layerhaving a multiple δ-doped layer formed on the surface region of the well region; a contact region; a gate insulating film; and a gate electrode. The accumulation channel layerhas a structure in which undoped layersand δ-doped layersallowing spreading movement of carriers to the undoped layersunder a quantum effect are alternately stacked. A source electrodeis provided which enters into the accumulation channel layerand the contact regionto come into direct contact with the contact region. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.