The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2009

Filed:

Sep. 22, 2006
Applicants:

Tien-ler Lin, Saratoga, CA (US);

Kwangho Kim, Pleasanton, CA (US);

Hui Chen, Santa Clara, CA (US);

Eungjoon Park, Fremont, CA (US);

Inventors:

Tien-Ler Lin, Saratoga, CA (US);

Kwangho Kim, Pleasanton, CA (US);

Hui Chen, Santa Clara, CA (US);

Eungjoon Park, Fremont, CA (US);

Assignee:

Winbond Electronics Corporation, Hsinchu, Taiwan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/34 (2006.01); G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.


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