The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
Oct. 05, 2006
Byeong Y. Kim, LaGrangeville, NY (US);
Xiaomeng Chen, Poughkeepsie, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Christopher D. Sheraw, Poughkeepsie, NY (US);
Linda Black, Wappingers Falls, NY (US);
Igor Peidous, Fishkill, NY (US);
Byeong Y. Kim, LaGrangeville, NY (US);
Xiaomeng Chen, Poughkeepsie, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Christopher D. Sheraw, Poughkeepsie, NY (US);
Linda Black, Wappingers Falls, NY (US);
Igor Peidous, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Advanced Micro Devices, Inc. (AMD), Sunnyvale, CA (US);
Abstract
Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.