The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
Apr. 06, 2007
Sheng-chieh Liu, Taichung, TW;
Tzu-yang Wu, Hsinchu, TW;
Ya-wen Lee, Taichung, TW;
Jeffery Chu, Taipei, TW;
Hsueh-liang Chou, Jhubei, TW;
Chia-hung Kao, Budai Town, TW;
Sheng-Chieh Liu, Taichung, TW;
Tzu-Yang Wu, Hsinchu, TW;
Ya-Wen Lee, Taichung, TW;
Jeffery Chu, Taipei, TW;
Hsueh-Liang Chou, Jhubei, TW;
Chia-Hung Kao, Budai Town, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.