The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2009
Filed:
May. 12, 2006
Thomas S. Barnett, Jericho, VT (US);
Jeanne P. Bickford, Essex Junction, VT (US);
William Y. Chang, Williston, VT (US);
Rashmi D. Chatty, Williston, VT (US);
Sebnem Jaji, Flower Mound, TX (US);
Kerry A. Kravec, Wappingers Falls, NY (US);
Wing L. Lai, Williston, VT (US);
Gie Lee, Colchester, VT (US);
Brian M. Trapp, Poughkeepsie, NY (US);
Alan J. Weger, Mohegan Lake, NY (US);
Thomas S. Barnett, Jericho, VT (US);
Jeanne P. Bickford, Essex Junction, VT (US);
William Y. Chang, Williston, VT (US);
Rashmi D. Chatty, Williston, VT (US);
Sebnem Jaji, Flower Mound, TX (US);
Kerry A. Kravec, Wappingers Falls, NY (US);
Wing L. Lai, Williston, VT (US);
Gie Lee, Colchester, VT (US);
Brian M. Trapp, Poughkeepsie, NY (US);
Alan J. Weger, Mohegan Lake, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.