The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Oct. 16, 2006
Riichiro Shirota, Fujisawa, JP;
Fumitaka Arai, Yokohama, JP;
Toshiyuki Enda, Zushi, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Naoki Kusunoki, Fuchu, JP;
Nobutoshi Aoki, Yokohama, JP;
Makoto Mizukami, Kawasaki, JP;
Kiyotaka Miyano, Shinagawa-ku, JP;
Ichiro Mizushima, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Fumitaka Arai, Yokohama, JP;
Toshiyuki Enda, Zushi, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Naoki Kusunoki, Fuchu, JP;
Nobutoshi Aoki, Yokohama, JP;
Makoto Mizukami, Kawasaki, JP;
Kiyotaka Miyano, Shinagawa-ku, JP;
Ichiro Mizushima, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.