The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2008
Filed:
Dec. 23, 2004
Chuichi Miyazaki, Akishima, JP;
Yoshiyuki Abe, Hinode, JP;
Toshihide Uematsu, Hinode, JP;
Minoru Kimura, Tachikawa, JP;
Kazunari Suzuki, Ota, JP;
Masao Odagiri, Musashimurayama, JP;
Hideyuki Suga, Hamura, JP;
Manabu Takata, Hamura, JP;
Chuichi Miyazaki, Akishima, JP;
Yoshiyuki Abe, Hinode, JP;
Toshihide Uematsu, Hinode, JP;
Minoru Kimura, Tachikawa, JP;
Kazunari Suzuki, Ota, JP;
Masao Odagiri, Musashimurayama, JP;
Hideyuki Suga, Hamura, JP;
Manabu Takata, Hamura, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.