The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2008
Filed:
Mar. 29, 2007
Yi-lung Cheng, Danshuei Township, TW;
Bi-ling Liu, Hsin-Chu, TW;
Chin-chuang Peng, Hsin-Chu, TW;
Chien-shih Tsai, Hsin-Chu, TW;
Hway-chi Lin, Hsin-Chu, TW;
Yi-Lung Cheng, Danshuei Township, TW;
Bi-Ling Liu, Hsin-Chu, TW;
Chin-Chuang Peng, Hsin-Chu, TW;
Chien-Shih Tsai, Hsin-Chu, TW;
Hway-Chi Lin, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.