The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2008

Filed:

Dec. 21, 2005
Applicants:

Gab-jin Nam, Seoul, KR;

Young-sun Kim, Gyeonggi-do, KR;

Cha-young Yoo, Gyeonggi-do, KR;

Jong-cheol Lee, Seoul, KR;

Jin-tae Noh, Gyeonggi-do, KR;

Jae-young Ahn, Gyeonggi-do, KR;

Young-geun Park, Gyeonggi-do, KR;

Jae-hyoung Choi, Gyeonggi-do, KR;

Jae-hyun Yeo, Gyeonggi-do, KR;

Inventors:

Gab-Jin Nam, Seoul, KR;

Young-Sun Kim, Gyeonggi-do, KR;

Cha-Young Yoo, Gyeonggi-do, KR;

Jong-Cheol Lee, Seoul, KR;

Jin-Tae Noh, Gyeonggi-do, KR;

Jae-Young Ahn, Gyeonggi-do, KR;

Young-Geun Park, Gyeonggi-do, KR;

Jae-Hyoung Choi, Gyeonggi-do, KR;

Jae-Hyun Yeo, Gyeonggi-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.


Find Patent Forward Citations

Loading…