The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2008
Filed:
Aug. 13, 2007
Yalin Xiong, Union City, CA (US);
Zain K. Saidin, San Mateo, CA (US);
Sterling G. Watson, Palo Alto, CA (US);
Yalin Xiong, Union City, CA (US);
Zain K. Saidin, San Mateo, CA (US);
Sterling G. Watson, Palo Alto, CA (US);
KLA-Tencor Technologies Corporation, Milpitas, CA (US);
Abstract
Disclosed are techniques and apparatus for accounting for differing levels of defect susceptibility in different pattern areas of a reticle in an inspection of such reticle or in inspection of a semiconductor device fabricated from such reticle. In general terms, two or more areas of a reticle are analyzed to quantify each area's susceptibility to defects on the final semiconductor product. That is, each reticle area is analyzed and given a quantified defect susceptibility value, such as a MEEF (mask error enhancement factor) value. Such analysis includes analysis of an image that is estimated to result from the lithography tool which is to be utilized to expose semiconductor devices with the reticle. The defect susceptibility value generally depends on the reticle area's density and whether the correspond area of the estimated lithography image has intensity values which are proximate to an exposure threshold for a particular resist material to be used on the final semiconductor device. The quantified defect susceptibility for each reticle area is then used to selectively set the inspection sensitivity for each reticle area or its corresponding semiconductor device region. The reticle and/or resulting semiconductor device may then be inspected based on the selected sensitivity levels for the different areas of the sample under test.