The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7436729 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 14, 2008

Filed:

Oct. 04, 2005
Applicants:

Hiroyasu Yoshida, Tokyo, JP;

Kanji Oishi, Tokyo, JP;

Naohisa Nishioka, Tokyo, JP;

Inventors:

Hiroyasu Yoshida, Tokyo, JP;

Kanji Oishi, Tokyo, JP;

Naohisa Nishioka, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

A fuse circuit uses an electrically writable fuse circuit and comprises a first fuse unit provided with a first electrically writable fuse, and a second fuse unit provided with a second electrically writable fuse, and the state of logical add of the states of the first and second fuse units is used as the output of the electrically writable fuse circuit in the first and second fuse units. Reliability in writing in of the fuse can be improved by using such a fuse circuit for a redundancy decoder circuit or the like.


Find Patent Forward Citations

Yoshida, Hiroyasu. (2008). Fuse circuit and semiconductor device using fuse circuit thereof (U.S. Patent No. 7436729). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7436729

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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