The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2008
Filed:
Dec. 29, 2005
Derryl D. J. Allman, Camas, WA (US);
Hemanshu D. Bhatt, Vancouver, WA (US);
Charles E. May, Fairview, OR (US);
Peter Austin Burke, Portland, OR (US);
Byung-sung Kwak, Portland, OR (US);
Sey-shing Sun, Portland, OR (US);
David T. Price, Gresham, OR (US);
David Pritchard, Saxony, DE;
Derryl D. J. Allman, Camas, WA (US);
Hemanshu D. Bhatt, Vancouver, WA (US);
Charles E. May, Fairview, OR (US);
Peter Austin Burke, Portland, OR (US);
Byung-Sung Kwak, Portland, OR (US);
Sey-Shing Sun, Portland, OR (US);
David T. Price, Gresham, OR (US);
David Pritchard, Saxony, DE;
LSI Corporation, Milpitas, CA (US);
Abstract
A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.