The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2008
Filed:
Dec. 30, 2005
Woo-yeong Cho, Hwaseong-si, KR;
Du-eung Kim, Yongin-si, KR;
Yun-seung Shin, Seoul, KR;
Hyun-geun Byun, Yongin-si, KR;
Sang-beom Kang, Hwaseong-si, KR;
Beak-hyung Cho, Hwaseong-si, KR;
Choong-keun Kwak, Suwon-si, KR;
Woo-Yeong Cho, Hwaseong-si, KR;
Du-Eung Kim, Yongin-si, KR;
Yun-Seung Shin, Seoul, KR;
Hyun-Geun Byun, Yongin-si, KR;
Sang-Beom Kang, Hwaseong-si, KR;
Beak-Hyung Cho, Hwaseong-si, KR;
Choong-Keun Kwak, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.