The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2008
Filed:
Jan. 30, 2002
Jung-cheun Lien, San Jose, CA (US);
Chung-yuan Sun, San Jose, CA (US);
Tong Liu, San Jose, CA (US);
Zili Zhang, Fremont, CA (US);
Sheng Feng, Cupertino, CA (US);
Eddy C. Huang, San Jose, CA (US);
Naihui Liao, Taipei, TW;
Jung-Cheun Lien, San Jose, CA (US);
Chung-Yuan Sun, San Jose, CA (US);
Tong Liu, San Jose, CA (US);
Zili Zhang, Fremont, CA (US);
Sheng Feng, Cupertino, CA (US);
Eddy C. Huang, San Jose, CA (US);
Naihui Liao, Taipei, TW;
Actel Corporation, Mountain View, CA (US);
Abstract
A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks, defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks, determining an expected logic result for a selected logical combination of the individual test inputs, applying the individual test inputs to the first end of each of the at least two of the first sets of tracks, performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result, and flagging an error if the actual result is not identical with the expected logic result.