The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2008
Filed:
Dec. 30, 2005
Jung-chih Tsao, Taipei, TW;
Kei-wei Chen, Yung-ho, TW;
Ying-jing LU, Daliao Township, Kaohsiung County, TW;
Yu-sheng Wang, Tainan, TW;
Yu-ku Lin, Hsinchu, TW;
Jung-Chih Tsao, Taipei, TW;
Kei-Wei Chen, Yung-ho, TW;
Ying-Jing Lu, Daliao Township, Kaohsiung County, TW;
Yu-Sheng Wang, Tainan, TW;
Yu-Ku Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;
Abstract
Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.