The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7417314 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 26, 2008

Filed:

Nov. 27, 2006
Applicants:

Charles W. C. Lin, Singapore, SG;

Cheng-chung Chen, Taipei, TW;

Cheng-lien Chiang, Taipei, TW;

Inventors:

Charles W. C. Lin, Singapore, SG;

Cheng-Chung Chen, Taipei, TW;

Cheng-Lien Chiang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a filler, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line is adjacent to the bumped terminal and extends laterally beyond the bumped terminal and the filler, and the filler contacts the bumped terminal in a cavity that extends through the bumped terminal.


Find Patent Forward Citations

Lin, Charles W. C.. (2008). Semiconductor chip assembly with laterally aligned bumped terminal and filler (U.S. Patent No. 7417314). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7417314

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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