The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2008
Filed:
May. 03, 2006
Satoshi Torii, Sunnyvale, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Youseok Suh, Cupertino, CA (US);
Lei Xue, Sunnyvale, CA (US);
Satoshi Torii, Sunnyvale, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Youseok Suh, Cupertino, CA (US);
Lei Xue, Sunnyvale, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.