The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2008
Filed:
May. 19, 2006
Qing MA, San Jose, CA (US);
Jin Lee, Mountain View, CA (US);
Harry Fujimoto, Sunnyvale, CA (US);
Changhong Dai, San Jose, CA (US);
Shiuh-wuu Lee, San Jose, CA (US);
Travis Eiles, San Jose, CA (US);
Krishna Seshan, San Jose, CA (US);
Qing Ma, San Jose, CA (US);
Jin Lee, Mountain View, CA (US);
Harry Fujimoto, Sunnyvale, CA (US);
Changhong Dai, San Jose, CA (US);
Shiuh-Wuu Lee, San Jose, CA (US);
Travis Eiles, San Jose, CA (US);
Krishna Seshan, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.