The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2008
Filed:
Apr. 21, 2006
Scott D. Allen, Ledgewood, NJ (US);
Cyril Cabral, Jr., Mahopac, NY (US);
Kevin K. Dezfulian, Mount Kisco, NY (US);
Sunfei Fang, LaGrangeville, NY (US);
Brian J. Greene, Danbury, CT (US);
Rajarao Jammy, Hopewell Junction, NY (US);
Christian Lavoie, Ossinging, NY (US);
Zhijiong Luo, Carmel, NY (US);
Hung NG, New Milford, NJ (US);
Chun-yung Sung, Poughkeepsie, NY (US);
Clement H. Wann, Carmel, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Scott D. Allen, Ledgewood, NJ (US);
Cyril Cabral, Jr., Mahopac, NY (US);
Kevin K. Dezfulian, Mount Kisco, NY (US);
Sunfei Fang, LaGrangeville, NY (US);
Brian J. Greene, Danbury, CT (US);
Rajarao Jammy, Hopewell Junction, NY (US);
Christian Lavoie, Ossinging, NY (US);
Zhijiong Luo, Carmel, NY (US);
Hung Ng, New Milford, NJ (US);
Chun-Yung Sung, Poughkeepsie, NY (US);
Clement H. Wann, Carmel, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.