The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2008
Filed:
Apr. 26, 2005
Toshihide Nabatame, Tsukuba, JP;
Akira Toriumi, Yokohama, JP;
Tsuyoshi Horikawa, Tsukuba, JP;
Kunihiko Iwamoto, Kyoto, JP;
Koji Tominaga, Kyoto, JP;
Toshihide Nabatame, Tsukuba, JP;
Akira Toriumi, Yokohama, JP;
Tsuyoshi Horikawa, Tsukuba, JP;
Kunihiko Iwamoto, Kyoto, JP;
Koji Tominaga, Kyoto, JP;
Renesas Technology Corporation, Tokyo, JP;
National Institute of Advanced Industrial Science and Technology, Tokyo, JP;
Rohm Co., Ltd., Kyoto, JP;
Horiba., Ltd., Kyoto, JP;
Abstract
To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.