The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2008
Filed:
Jun. 30, 2005
Gökhan Percin, Los Gatos, CA (US);
Ram Ramanujam, Santa Cruz, CA (US);
Franz Xaver Zach, Los Gatos, CA (US);
Koichi Suzuki, Tokyo, JP;
Gökhan Percin, Los Gatos, CA (US);
Ram Ramanujam, Santa Cruz, CA (US);
Franz Xaver Zach, Los Gatos, CA (US);
Koichi Suzuki, Tokyo, JP;
Invarium, Inc., San Jose, CA (US);
Abstract
This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, the model is calibrated using the measurements obtained by running wafers through the same lithography, patterning, and etch processes. In this invention, a novel real time method for verifying and monitoring the calibrated model on a production or monitor wafer is presented: optical proximity corrected (OPC-ed) test and verification structures are placed on scribe lines or cut lines of the production or monitor wafer, and with pre-determined schedule, the critical dimensions and images of these test and verification structures are monitored across wafer and across exposure field.