The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2008
Filed:
May. 07, 2004
Sung-min Kim, Incheon, KR;
Dong-gun Park, Gyeonggi-do, KR;
Chang-sub Lee, Gyeonggi-do, KR;
Jeong-dong Choe, Gyeonggi-do, KR;
Shin-ae Lee, Gyeonggi-do, KR;
Seong-ho Kim, Gyeonggi-do, KR;
Sung-Min Kim, Incheon, KR;
Dong-Gun Park, Gyeonggi-do, KR;
Chang-Sub Lee, Gyeonggi-do, KR;
Jeong-Dong Choe, Gyeonggi-do, KR;
Shin-Ae Lee, Gyeonggi-do, KR;
Seong-Ho Kim, Gyeonggi-do, KR;
Abstract
Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.