The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2008
Filed:
Apr. 20, 2005
Yuan Yuan, Austin, TX (US);
Kevin J. Hess, Austin, TX (US);
Chu-chung Lee, Round Rock, TX (US);
Tu-anh Tran, Austin, TX (US);
Donna Woosley, Legal Representative, Austin, TX (US);
Yuan Yuan, Austin, TX (US);
Kevin J. Hess, Austin, TX (US);
Chu-Chung Lee, Round Rock, TX (US);
Tu-Anh Tran, Austin, TX (US);
Donna Woosley, legal representative, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.