The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Dec. 09, 2002
Chu-yun Fu, Taipei, TW;
Chi-hsun Hsieh, Changhua, TW;
Yi-ming Sheu, Hsin Chu, TW;
Syun-ming Jang, Hsin-Chu, TW;
Chu-Yun Fu, Taipei, TW;
Chi-Hsun Hsieh, Changhua, TW;
Yi-Ming Sheu, Hsin Chu, TW;
Syun-Ming Jang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NHflow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NHand SiHflow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.