The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Mar. 31, 2004
Yang Cao, Beaverton, OR (US);
Yue MA, Hillsboro, OR (US);
Jir-shyr Chen, Beavergon, OR (US);
Rajiv Rastogi, Portland, OR (US);
Yang Cao, Beaverton, OR (US);
Yue Ma, Hillsboro, OR (US);
Jir-shyr Chen, Beavergon, OR (US);
Rajiv Rastogi, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage. In one embodiment, the voltage of a plating cell including a reference wafer which has substantially complete Cu seed coverage is measured. A reference resistance of the plating cell with the reference wafer is determined. The voltage of the plating cell including a calibration wafer which has no or insufficient seed coverage at its edge is measured. A calibration resistance of the plating cell with the calibration wafer is determined. An error trigger based on a comparison of the reference resistance with the calibration resistance is selected.