The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2008

Filed:

Oct. 22, 2004
Applicants:

Joel A. Auernheimer, Phoenix, AZ (US);

Nicholas L. Holmberg, Gilbert, AZ (US);

Kaladhar Radhakrishnan, Chandler, AZ (US);

Dustin P. Wood, Chandler, AZ (US);

Inventors:

Joel A. Auernheimer, Phoenix, AZ (US);

Nicholas L. Holmberg, Gilbert, AZ (US);

Kaladhar Radhakrishnan, Chandler, AZ (US);

Dustin P. Wood, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/495 (2006.01); H01L 27/06 (2006.01); H01L 27/07 (2006.01); H01L 21/50 (2006.01); H01L 21/48 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.


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