The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2008
Filed:
Mar. 16, 2006
Chun-chieh Lin, Hsin-Chu, TW;
Wen-chin Lee, Hsin-Chu, TW;
Chenming HU, Hsin-Chu, TW;
Shang-chih Chen, Hsin-Chu, TW;
Chih-hao Wang, Hsin-Chu, TW;
Fu-liaog Yang, Hsin-Chu, TW;
Yee-chia Yeo, Hsin-Chu, TW;
Chun-Chieh Lin, Hsin-Chu, TW;
Wen-Chin Lee, Hsin-Chu, TW;
Chenming Hu, Hsin-Chu, TW;
Shang-Chih Chen, Hsin-Chu, TW;
Chih-Hao Wang, Hsin-Chu, TW;
Fu-Liaog Yang, Hsin-Chu, TW;
Yee-Chia Yeo, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.