The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7352890 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 01, 2008

Filed:

Feb. 17, 2006
Applicants:

Atsushi Shimoda, Hiratsuka, JP;

Ichirou Ishimaru, Mure, JP;

Yuji Takagi, Kamakura, JP;

Takuo Tamura, Yokohama, JP;

Yuichi Hamamura, Yokohama, JP;

Kenji Watanabe, Oume, JP;

Yasuhiko Ozawa, Abiko, JP;

Seiji Isogai, Hitachinaka, JP;

Inventors:

Atsushi Shimoda, Hiratsuka, JP;

Ichirou Ishimaru, Mure, JP;

Yuji Takagi, Kamakura, JP;

Takuo Tamura, Yokohama, JP;

Yuichi Hamamura, Yokohama, JP;

Kenji Watanabe, Oume, JP;

Yasuhiko Ozawa, Abiko, JP;

Seiji Isogai, Hitachinaka, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for analyzing defects in electronic circuit patterns, including: comparing position information of structural defects with position information of electrical faults and extracting corroborated defects having common position information between the structural defects and electrical faults; classifying images of extracted corroborated defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of defects, and results of performing an electronic test; modifying the pre-stored classification rule by correcting classification of classified defect images displayed on the screen; and repeating the operations for each subsequent object, wherein for each present object under inspection, using a modified pre-stored classification rule with respect to a previous object, as the pre-stored classification rule for the operations with respect to the present object.


Find Patent Forward Citations

Shimoda, Atsushi. (2008). Method for analyzing circuit pattern defects and a system thereof (U.S. Patent No. 7352890). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7352890

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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